A phantom circuit is formed by connections to the centre taps of a pair of transformers at a transmit end, which pair of transformers are linked by respective communication links to a pair of transformers at a receive end, connections to the centre taps of the transformers at the receive end forming the other end of the phantom circuit. The communication links between the two transformers of the transmit end and the two transformers of the receive end form two high speed communication links and the phantom circuit provides a further low speed communication link. Thus advantageously phantom circuits provide an additional communications link without the provision of additional communications link circuitry.
Typically the communication links formed by the respective pairs of transformers will transmit high speed data, typically between computers. The phantom circuit cannot support high speed communication such as that between computers, but can advantageously be used in accordance with the present invention to distribute power from a transmit end to a receive end; the phantom circuit being used to supply power to devices to which the high speed communication links are connected.
Thus according to the present invention there is provided a communication system comprising:
a first high speed link having a first transformer interface at a transmit end and a second transformer interface at a receive end; PA1 a second high speed link having a third transformer interface at a transmit end and a fourth transformer interface at a receive end; PA1 a low speed link comprising a phantom circuit formed by the first to fourth transformers, the transmit end of the low speed link being formed by connections to the centre taps of the first and third transformers and the receive end of the low speed link being formed by connections to the centre taps of the second and fourth transformers; PA1 wherein the transmit end of the low speed link is connected to a power supply and at least one of the high speed links is connected to a device at the receive end for receiving signals from the respective high speed link, the receive end of the low speed link providing power to the device from the power supply. PA1 output circuitry for providing two parallel outputs, one in the form of a data signal and one in the form of a strobe signal and including strobe generation circuitry, wherein the data signal comprises a serial bit pattern and the strobe generation circuitry generates the strobe signal such that the strobe signal has signal transitions only at bit boundaries where there is no transition on the data signal, the strobe generation circuitry being controlled by a clock signal such that for each clock pulse where there is no signal transition in the data signal a signal transition is generated in the strobe signal, the frequency of the clock signal being continuously variable; and PA1 input circuitry having two inputs for receiving data and strobe signals, and including an exclusive-or circuit for receiving the data and strobe signals and generating a receive clock on the output thereof, the receive clock being generated with clock signal transitions having a timing matching that at which the strobe and data signal s were transmitted. PA1 input circuitry having two inputs, one input for receiving a data signal and the other input for receiving a strobe signal, the strobe signal being parallel to the data signal and having signal transitions only at bit boundaries where there is no transition on the data signal; PA1 an exclusive-or gate, having inputs connected to the two inputs, and generating a receive clock on the output thereof; PA1 detection circuitry having two inputs coupled to the respective two inputs of the input circuitry and for detecting an expected bit sequence associated with the data signal on one of said two inputs; PA1 output circuitry for outputting the data signal under the control of the receive clock; and PA1 selection circuitry for connecting the one of said inputs on which said sequence is detected to the output circuit. PA1 outputting a binary data signal; PA1 generating and outputting a binary strobe signal, parallel to the binary data signal, having signal transitions only at bit boundaries where there is no transition on the parallel binary data signal; and PA1 encoding the binary data signal and the binary strobe signal into respective ternary dc balanced signals for transmission. PA1 calculating the running digital sum of the ternary signal; PA1 transmitting next binary 1 as ternary -1 if the running digital sum is positive and at least two 0's have been transmitted since the last ternary +1; PA1 transmitting the next binary 1 as ternary +1 if the running digital sum is negative and at least two 0's have been transmitted since the last ternary -1; PA1 transmitting at least two successive binary 1's as ternary -1's if the running digital sum is positive and the at least two binary 1's follow any number of 0's; PA1 transmitting at least two successive binary 1's as ternary +1's if the running digital sum is negative and the at least two binary 1's follow any number of 0's; and PA1 otherwise reversing the polarity of each ternary 1 each time a run of at least one 0 occurs. PA1 input circuitry for receiving a binary data signal; PA1 strobe generation circuitry for generating a binary strobe signal, parallel to the binary data signal, and having signal transitions only at bit boundaries where there is no transition on the parallel binary data signal; PA1 encoding circuitry for encoding the binary data and strobe signals into respective ternary dc balanced signals; and PA1 output circuitry for transmitting the ternary encoded data and strobe signals. PA1 rectifying the ternary data and strobe signals to generate binary data and strobe signals; PA1 exclusive-ORing the data and strobe signals to generate a receive clock; and PA1 outputting the rectified data signals under the control of the receive clock. PA1 input circuitry for receiving a ternary data signal and a ternary strobe signal, the strobe signal being parallel to the data signal and having signal transitions only at bit boundaries where there is no transition on the data signal; PA1 rectification circuitry for rectifying the ternary data and strobe signals and generating binary data and strobe signals; PA1 an exclusive-OR gate for receiving the data and strobe signals and generating the receive clock at its output; and PA1 output circuitry for outputting the binary data signal under the control of the receive clock.
Preferably one of the high speed links transmits a serial data signal, and the other high speed link transmits a strobe signal having transitions only at bit boundaries of the data signal where there are no transitions, thus forming a data-strobe communication link as disclosed in earlier European Patent Application Publication No. 0458648.
In addition to the distribution of power, the phantom circuit may be used to transmit low speed signals. The phantom circuit may also be used to distribute a global signalling clock. The global signalling clock may be implemented by providing a switch on the transmit side of the phantom circuit which switches the power supply for transmission in and out of the phantom circuit.
The phantom circuits may also be used to distribute power to remote destinations where there are no devices for receiving high speed communication signals.
The present invention also relates to a communication system in which a variable frequency clock is used in the transmission circuit. The invention is particularly, but not exclusively, concerned with the use of spread spectrum clocks in the transmission circuits of communications systems.
For communication networks, particularly those implemented in the home, there is a need to minimise electromagnetic radiation. The use of spread spectrum clocks reduces the peaks of electromagnetic radiation at harmonics of the clock frequency, and thus it would be advantageous to employ a variable frequency clock such as a spread spectrum clock in any communication system utilising a high speed network, particularly in the home.